RISC-V for HPC SC26 workshop

The RISC-V for HPC Workshop, co-located with the International Conference for High Performance Computing (SC26), investigates the potential of the open RISC-V instruction set architecture as a platform for high-performance and exascale computing. Topics include custom processor extensions for scientific workloads, RISC-V-based accelerator designs, AI and machine learning on RISC-V hardware, and the ecosystem tools enabling open-architecture supercomputing. It brings together HPC architects, system designers, and application scientists to advance open-hardware computing at scale.

Categories RISC-V HPC exascale AI